Non-volatile memories, in which the data is rewritable, are now widely used. In the technical field of non-volatile memories, techniques for increasing the number of bits per unit area and reducing the cost per bit have been developed.
A non-volatile flash memory generally employs a floating-gate flash memory having an array architecture such as of a NOR type or NAND type. A NOR-type floating-gate flash memory has a random access feature, yet it is difficult to increase the density thereof, because a bit line contact has to be provided in each cell. On the other hand, in a NAND-type floating-gate flash memory, the cells can be connected in series to reduce the number of the bit line contacts, enabling high-density cell arrangement, yet the cells cannot be accessed randomly. In addition, it is not easy to reduce the thickness of the tunnel insulating film in a floating-gate flash memory. This is a technical drawback in increasing the capacity of the memory.
In order to deal with the above-mentioned drawbacks, there is a well-known method of changing the threshold value of a floating-gate flash memory, according to the quantity of electric charge for storing multi-level data in one cell. In a memory cell of this type, at least one portion of the gate insulating film is made with a material having electron-trapping properties so that a change in the threshold value of a cell-transistor can be read by controlling the quantity of electric charge trapped in the aforementioned one portion. In contrast, a normal floating-gate flash memory spatially stores the charge uniformly in the floating gate so that the change in the threshold value can be read by controlling the quantity of the stored charge. Specifically, the gate insulating film provided immediately below the gate electrode is configured to have an ON structure or ONO stack. The charge is partially stored in a Si3N4 film provided near the source/drain of the transistor. This makes it possible to store two-bit data in one cell. A SONOS type memory having buried bit lines is known as the aforementioned type of memory. The stored charge is not necessarily provided uniformly in terms of space in the insulating film. Instead, its non-uniformity is due to the non-uniform injection of charge.
When the SONOS type memory cell architecture having buried bit lines is compared to the floating-gate memory cell having buried bit lines, the method of retaining the electric charge is different. In addition, there is another difference in that the SONOS type memory having buried bit lines employs source lines and bit lines that operate in the same manner, although both types have memory cells with buried bit lines. Here, the bit line serves as the source or drain in each cell in the SONOS type memory having buried bit lines. Hence, in the following description, the bit line shall also denote the source and drain of the cell.
The above-mentioned SONOS type memory having buried bit lines has a simple architecture compared to that of the floating-gate memory cell and can be accessed randomly. Moreover, the array thereof has a contactless structure. Two-bit information can be stored in one cell, and accordingly high-density information can be stored (the cell area can be downsized by approximately ½). SONOS type memories having buried lines are extremely useful devices in industry. The buried bit line structure denotes an array structure of the NOR type memory, yet does not require a bit line contact window in each transistor because a source/drain diffusion layer serves as the bit line of the SONOS type memory below a word line.
FIGS. 1A through 1H are cross-sectional views illustrating a conventional fabrication process for forming a multi-level cell of the SONOS type having buried bit lines. It comprises a semiconductor substrate 100, an insulating film such as a nitride film 101, well regions 102 and 103, a trench groove 110 for element isolation, an insulating film 111 for element isolation, a resist pattern 112 for forming element isolation, a tunnel insulating film 121, a nitride film 122 for storage, an upper oxide film 123 of an ONO stack, a diffusion layer bit line 124, gate oxide films 131 and 132, a gate electrode 151, a contact hole 161, and wiring 162. In this conventional example, shallow trench isolation (STI) is employed for element isolation in a peripheral circuit. In addition, a memory cell array region (core region) has a planar structure. On the other hand, the periphery circuit has a CMOS structure, and the core region and the peripheral circuit region have different structures.
Referring to FIG. 1A, the insulating film 101 is formed on a main surface of semiconductor substrate 100, and a resist pattern 112 is formed on insulating film 101 using photolithography techniques. Etching techniques provide trench grooves 110 for element isolation. For example, substrate 100 is a p-type semiconductor. The Si3N4 film is grown to a thickness of approximately 100 nm and serves as the insulating film 101. The resist is applied to pattern the film. Resist pattern 112 is used as a mask for element isolation in order to etch certain portions of the Si3N4 film and the semiconductor substrate to form trench groove 110 having a depth of approximately 350 nm.
Next, resist pattern 112 is removed, and a buried insulating film is grown on the main surface of semiconductor substrate 100. A CMP process is carried out to expose insulating film 101. The aforementioned buried insulating film is polished and only remains inside the trench groove 110 to form the insulating film 111 for element isolation. After the insulating film 111 is formed, insulating film 101 is removed (FIG. 1B). For example, a HDP (high-density plasma) oxide film having the thickness of 550 nm is employed for the buried insulating film. The insulating film 101 of Si3N4 is removed by etching with phosphoric acid. Subsequently, the well regions 102 and 103 are formed in the peripheral circuit region by ion implantation (FIG. 1C). This process is performed in such a manner that, for example, the resist is applied and patterned and then ions of phosphor are implanted using the resist pattern as a mask. After phosphorous ions are implanted, boron ions may be implanted to form a triple well structure in well region 103.
Further, the tunnel insulating film 121, the nitride film 122 for storage, and the upper oxide film 123 are successively stacked to form the ONO stack. Openings are provided on given portions in the aforementioned ONO stack for forming the bit line of diffusion layer 124 using photolithography techniques. Ions are then implanted through openings to form the bit line of diffusion layer 124 (FIG. 1D). In this process, for example, a tunnel oxide film having the thickness of approximately 7 nm is formed by thermally oxidizing the main surface of semiconductor substrate 100, where the insulating film has been removed from the core region and the peripheral circuit region by HF. A nitride film having a thickness of approximately 10 nm is deposited on the tunnel oxide film using a CVD process. Moreover, the surface of the nitride film is thermally oxidized to form an upper oxide film having a thickness of approximately 10 nm. Thus, the ONO stack is formed in this manner. In addition, arsenic ions are implanted from the openings to create the bit line of the diffusion layer at a concentration of approximately 1.0×1015 cm−2 and an accelerating voltage of 50 KeV. The above-mentioned ONO stack is formed not only in the core region, but also in the peripheral circuit region. The ONO stack is not needed in the peripheral circuit region. Thus, the ONO stack provided in the peripheral circuit region is removed using resist patterning techniques (FIG. 1E).
The gate insulating films 131 and 132, which are different in thickness, are formed in the periphery circuit by thermal oxidization (FIG. 1F). In order to form these gate insulating films 131 and 132, for example, a gate insulating film having a thickness of approximately 8 nm is first formed by a thermal process at approximately 900° C. The resist is patterned and removed using HF, and the thermal oxidization is again conducted at approximately 900° C. to form a thermally oxidized film having a thickness of approximately 10 nm. In this manner, it is possible to form the gate insulating films with two thicknesses; i.e., approximately 10 nm and 13 nm respectively.
After the aforementioned gate insulating films are formed, a conductive film is grown on the ONO stack and on the gate insulating film for the gate electrode. The resist is patterned and etched to form the word line and the gate electrodes 151 in the periphery circuit (FIG. 1G). This conductive film for the gate electrode is made, for example, of polysilicon having the thickness of approximately 180 nm, and is grown by a thermal CVD method. Finally, the source/drain regions are formed in the peripheral circuit region using resist patterning and ion implantation. A silicide may be formed, an interlayer insulating film may be grown, and the contact hole 161 and wiring 162 may be formed as necessary (FIG. 1H).
Following is a description of the operation of a conventional SONOS type cell-transistor in which one bit is contained per cell. That is, near the drain, hot electrons are generated during programming, and hot holes are generated by tunneling between bands during erasing. However, the electrons and holes are trapped in the gate insulating film. During reading, the source and drain are reversed and the difference in the threshold value is detected by the difference in the amount of positive and negative charge. In order to arrange the SONOS cells having one bit per cell at a high density, the above-mentioned architecture of buried bit lines is employed in the array. The bit line functions as the drain during programming and erasing, and functions as the source during reading. In the SONOS type planar memory cell with the buried bit lines, the ONO stack isolates the bit line of diffusion layer from the word line.
FIG. 2A is a schematic plan view of a SONOS type memory cell having buried bit lines. FIGS. 2B through FIG. 2E show cross-sectional views taken along lines A-A′, B-B′, C-C′, and D-D′ respectively shown in FIG. 2A. The drawings, show a word line WL 201, a bit line BL 202, a bit line contact 203, and a gate insulating film 204. This SONOS type of memory cell is a NOR type. Generally, one bit line contact 203 is provided for multiple world lines (WL: 201). The bit lines (diffusion layer) 202 are arranged below the word lines 201 through the gate insulating film 204.
However, the width of the line 202 becomes narrower as the cell is downsized. Also, the concentration of ion implantation should be reduced to avoid short channeling. Thus, the resistivity of the bit line of diffusion layer 202 becomes higher. As a result, the number of contacts must be increased because if resistivity of the bit line of diffusion layer 202 becomes higher, there arises a difference in the effective voltage applied to cells connected to the word line 201 next to the bit line contacts 203 and the effective voltage applied to the cells respectively connected to the word lines 201. This is due to the voltage effect of the current flowing through the bit lines; (for example, during programming). This results in the different characteristics between the cells depending on their distance from the bit line contact 203.
Therefore, in order to downsize the memory cell, for example, a layout with the bit line contact 203 provided for every 16 word lines has to be changed to another layout with a bit line contact 203 for every eight word lines. However, the technical features of a small cell area will be impaired, although the small cell area is an advantage of SONOS type memory cell with buried bit lines. To solve this problem, it would be desirable to provide a method of reducing the resistivity of the bit line of diffusion layer 202 without increasing the planar surface area of the bit line on the substrate surface.